Intels 8051 microcontroller having 128 bytes of user application RAM and an extra 128 bytes as SFR area. This RAM is divided into three1) Register banks
2) Bit and Byte addresable area
3) Scratch Pad RAM
The register bank is again divided into register bank0 (RB0),register bank 1 (RB1), register bank2(RB2) and register bank3 (RB3). Each register bank having registers R1,R2,R3,R4,R5,R6,R7.
But at a time one register bank is accessible. Either RB0 or RB1 or Rb2 or RB3. That if we are using R0 from RB0 we are restricted to use the R0 from rest of the banks. The RB0 is ranging from address 0x00 to 0x07, RB1 is from 0x08 to 0x10 , RB2 is from 0x10 to 0x17 and RB3 ,0x18 to 0x1F.
Or using the PSW register2) Bit and Byte addresable area
3) Scratch Pad RAM
The register bank is again divided into register bank0 (RB0),register bank 1 (RB1), register bank2(RB2) and register bank3 (RB3). Each register bank having registers R1,R2,R3,R4,R5,R6,R7.
But at a time one register bank is accessible. Either RB0 or RB1 or Rb2 or RB3. That if we are using R0 from RB0 we are restricted to use the R0 from rest of the banks. The RB0 is ranging from address 0x00 to 0x07, RB1 is from 0x08 to 0x10 , RB2 is from 0x10 to 0x17 and RB3 ,0x18 to 0x1F.
So here utilizing the addresses.
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